Polyphase logical circuit employing complementary misfet

ABSTRACT

A COMPLEMENTARY MOS LOGIC CIRCUIT HAS A REDUCED NUMBER OF TRANSISTORS. A P-CHANNEL MOSFET AND AN NCHANNEL MOSFET ARE CONNECTED IN SERIES WITH A LOGICAL BLOCK OF A PREDETERMINED LOGICAL EXPRESSIONS BETWEEN ONE TERMINAL OF A POWER SOURCE AND THE LOGICAL BLOCK AND BETWEEN THE LOGICAL BLOCK AND THE OTHER TERMINAL OF THE POWER SOURCE, RESPECTIVELY. MEANS IS PROVIDED WHICH DRIVES THE P-CHANNEL AND N-CHANNEL MOSFETS BY A FIRST CLOCK PULSE. MEANS IS PROVIDED WHICH ESTABLISHES A CURRENT PATH BETWEEN THE LOGICAL BLOCK AND AN OUTPUT TERMINAL OF THE COMPLEMENTARY MOS LOGICAL CIRCUIT OR BETWEEN THE CONNECTION POINT OF THE LOGICAL BLOCK AND P-CHANNEL MOSFET AND THE OUTPUT TERMINAL AT TIMINGS OF THE FIRST CLOCK PULSE AND A SECOND CLOCK PULSE DIFFERING IN PHASE THEREFROM.

DEFENSIVE PULIGATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 0.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent Office makes no assertion as to the novelty of the disclosed subject matter.

PUBLISHED SEPTEMBER 8, 1974 A complementary MOS logic circuit has a reduced number of transistors. A P-channel MOSFET and an N- channel MOSFET are connected in series with a logical block of a predetermined logical expression between one terminal of a power source and the logical block and between the logical block and the other terminal of the power source, respectively. Means is provided] which drives the P-channel and N-channel MOSFETs by a first clock pulse. Means is provided which establishes a current path between the logical block and an output terminal of the complementary MOS logical circuit or between the connection point of the logical block and P-channel MOSFET and the output terminal at timings of the first clock pulse and a second clock pulse differing in phase therefrom.

Sept. 3, 1974 53 NQMlYA ET AL T926,03

POLYPHASE LOGICAL CIRCUIT EMPLOYING COMPLEMENTARY MISFET'S Filed July 23. 1973 2 Sheets-Sheet 1 FIG. I

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Filed July 25. 1973 1974 55 NOMIYA E'TAL T926,003

POLYPHASE LOGICAL CIRCUIT EMPLOYING COMPLEMENTARY MISFET'S 2 Sheets-Sheet 2 FIG. 4

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